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240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb E version
This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version E based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
* JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3,4,5, 6 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK) * * * * * * * Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball FBGA(128Mx8), 84ball FBGA(64Mx16) 133.35 x 30.00 mm form factor RoHS compliant & Halogen-free
* * * * * * *
ORDERING INFORMATION
Part Name HMP164U6EFR8C-C4/Y5/S6/S5 HMP112U6EFR8C-C4/Y5/S6/S5 HMP112U7EFR8C-C4/Y5/S6/S5 HMP125U6EFR8C-C4/Y5/S6/S5 HMP125U7EFR8C-C4/Y5/S6/S5 Density 512MB 1GB 1GB 2GB 2GB Org. 64Mx64 128Mx64 128Mx72 256Mx64 256Mx72 # of DRAMs 4 8 9 16 18 # of ranks 1 1 1 2 2 Materials Halogen free Halogen free Halogen free Halogen free Halogen free ECC None None ECC None ECC
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Nov. 2008 1
1240pin DDR2 SDRAM Unbuffered DIMMs SPEED GRADE & KEY PARAMETERS
C4 (DDR2-533) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6 CL-tRCD-tRP 400 533 4-4-4 Y5 (DDR2-667) 400 533 667 5-5-5 S6 (DDR2-800) 533 667 800 6-6-6 S5 (DDR2-800) 400 533 800 5-5-5 Unit Mbps Mbps Mbps Mbps tCK
ADDRESS TABLE
Density 512MB 1GB 1GB 2GB 2GB Organization Ranks 64M x 64 128M x 64 128M x 72 256M x 64 256M x 72 1 1 1 2 2 SDRAMs 64Mb x 16 128Mb x 8 128Mb x 8 128Mb x 8 128Mb x 8 # of DRAMs 4 8 9 16 18 # of row/bank/column Address 13(A0~A12)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms
Rev. 0.3 / Nov. 2008
2
1240pin DDR2 SDRAM Unbuffered DIMMs Input/Output Functional Description
Symbol
CK[2:0], CK[2:0]
Type
SSTL
Polarity
Differential Crossing
Pin Description
CK and /CK are differential clock inputs. All the DDR2 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of /CK. Output (read) data is reference to the crossing of CK and /CK (Both directions of crossing) Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the
CKE[1:0]
SSTL
Active High
S[1:0]
SSTL
Active Low
command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
RAS, CAS, WE
ODT[1:0]
SSTL SSTL Supply Supply SSTL
Active Low Active High
/RAS,/CAS and /WE(ALONG WITH S) define the command being entered. Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 SDRAM mode register. Reference voltage for SSTL18 inputs Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
Vref VDDQ
BA[2:0]
-
Selects which DDR2 SDRAM internal bank of four or eight is activated. During a Bank Activate command cycle, Address input difines the row address(RA0~RA15) During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to
A[9:0], A10/AP, A[13:11]
SSTL
-
the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
DQ[63:0], CB[7:0]
SSTL
-
Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled
DM[8:0]
SSTL
Active High
High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. Data strobe for input and output data. For Rawcards using x16 organized DRAMs, DQ0~7 connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin of the DRAM These signals are tied at the system planar to either VSS or VDD to configure the serial SPD EEPROM. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister must be connected to VDD to act as a pull up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as a pull up on the system board. Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V.
VDD,VSS DQS[8:0], DQS[8:0] SA[2:0] SDA SCL VDDSPD
Supply Differential crossing Supply
SSTL
Rev. 0.3 / Nov. 2008
3
1240pin DDR2 SDRAM Unbuffered DIMMs PIN CONFIGURATION
Front Side
1 pin
64 pin 65 pin
120 pin
121 pin
184 pin 185 pin
240 pin
Back Side
PIN ASSIGNMENT
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Name VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS NC NC VSS DQ10 DQ11 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Name VSS NC(CB0)* NC(CB1)* VSS NC(DQS8)* NC(DQS8)* VSS NC(CB2)* NC(CB3)* VSS VDDQ CKE0 VDD BA2 NC VDDQ A11 A7 VDD A5 A4 VDDQ Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Name DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC,TEST1 Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Name VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS CK1 CK1 VSS DQ14 DQ15 VSS Pin 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 Name NC(CB4)* NC(CB5)* VSS NC(DM8)* NC VSS NC(CB6)* NC(CB7)* VSS VDDQ CKE1 VDD A15 A14 VDDQ A12 A9 VDD A8 A6 VDDQ A3 Pin 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 Name VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 CK2 VSS
* The pin names in parenthesises are applied to DIMM with ECC only.
Rev. 0.3 / Nov. 2008
4
1240pin DDR2 SDRAM Unbuffered DIMMs PIN ASSIGNMENT(Continued)
Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 Pin 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name A2 VDD VSS VSS VDD NC VDD A10/AP BA0 VDDQ WE CAS VDDQ S1 ODT1 VDDQ VSS DQ32 Pin 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Name DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS Pin 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Name A1 VDD CK0 CK0 VDD A0 VDD BA1 VDDQ RAS S0 VDDQ ODT0 A13 VDD VSS DQ36 DQ37 Pin 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Name DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
*NC = No connect
Note: 1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs). 2. NC Pins should not be connected to anything, including bussing within the NC group.
Rev. 0.3 / Nov. 2008
5
1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB(64Mbx64): HMP164U6EFR6C
/S 0
/ DQS 0 DQS 0 DM 0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
/ LD Q S LD Q S LD M
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS
/ DQS 4 DQS 4 DM 4 D Q 32 D Q 33 D Q 34 D Q 35 D Q 36 D Q 37 D Q 38 D Q 39 / DQS 5 DQS 5 DM 5 D Q 40 D Q 41 D Q 42 D Q 43 D Q 44 D Q 45 D Q 46 D Q 47
/ LDQ S LDQS LD M
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS
D0
D2
/ DQS 1 DQS 1 DM 1 DQ 8 DQ 9 D Q 10 D Q 11 D Q 12 D Q 13 D Q 14 D Q 15
/ UDQS UDQS UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
/ UDQS UDQS UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
/ DQS 2 DQS 2 DM 2 D Q 16 D Q 17 D Q 18 D Q 19 D Q 20 D Q 21 D Q 22 D Q 23
/ LDQS LDQS LD M
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS
/ DQS 6 DQS 6 DM 6 D Q 48 D Q 49 D Q 50 D Q 51 D Q 52 D Q 53 D Q 54 D Q 55
/ DQS 7 DQS 7 DM 7 D Q 56 D Q 57 D Q 58 D Q 59 D Q 60 D Q 61 D Q 62 D Q 63
/ LDQ S LDQS LD M
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS
D1
D3
/ DQS 3 DQS 3 DM 3 D Q 24 D Q 25 D Q 26 D Q 27 D Q 28 D Q 29 D Q 30 D Q 31
/ UDQS UDQS UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
/ UDQS UDQS UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
SCL
BA 0- BA 2 A 0 - A 12 / RAS / CAS CKE 0 /WE ODT 0
VD D S P D VD D / V D D Q V REF VS S
SCL WP A0 S A0
S erial P D A1 S A1
SDA
SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS
D0-D 3 D0-D 3 D0-D 3 D0-D 3 D0-D 3 D0-D 3 D0-D 3
A1 S A2
C lock S ignal Loads
C lock Input
C K 0, /C K 0
SDRAMs
NC
C K 1, /C K 1
S erial P D D O -D 3
2
C K 2, /C K 2
2
D O -D 3 D O -D 3
N otes: 1. D Q ,D M ,D Q S ,/D Q S resistors : 22 +/- 5 % . 2. B ax,A x,/R A S ,/C A S ,/W E resistors : 10 +/- 5 % .
Rev. 0.3 / Nov. 2008
6
1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM 1GB(128Mbx64): HMP112U6EFR8C
/S0 /DQS0 DQS0 DM0
DM /CS DQS /DQS
/DQS4 DQS4 DM4
DM /CS DQS /DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /DQS1 DQS1 DM1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 /DQS5 DQS5 DM5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /DQS2 DQS2 DM2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /DQS6 DQS6 DM6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 /DQS3 DQS3 DM3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 /DQS7 DQS7 DM7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
SCL
SCL WP Serial PD A0 A1 SA1 A1 SA2
Clock Signal Loads
SDA
Clock Input CK0, /CK0 CK1, /CK1 CK2, /CK2
SDRAMs 2 3 3
BA0-BA2 A0-A13 /RAS /CAS CKE0 /WE ODT0
SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7
SA0 VDD SPD VDD /VDDQ VREF VSS Serial PD DO-D7 DO-D7 DO-D7
Notes: 1. DQ,DM,DQS,/DQS resistors : 22 +/- 5 %. 2. Bax,Ax,/RAS,/CAS,/WE resistors : 5.1 +/- 5 %.
Rev. 0.3 / Nov. 2008
7
1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM 1GB(128Mbx72) - HMP112U7EFR8C
/S0
/DQS0 DQS0 DM0
DM /CS DQS /DQS
/DQS4 DQS4 DM4
DM /CS DQS /DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
/DQS1 DQS1 DM1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
/DQS5 DQS5 DM5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
/DQS2 DQS2 DM2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
/DQS6 DQS6 DM6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
/DQS3 DQS3 DM3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
/DQS7 DQS7 DM7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
/DQS8 DQS8 DM8
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
Clock Signal Loads
DM /CS DQS /DQS
SCL
SCL WP Serial PD A0 SA0 A1 SA1
A1 SA2
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
BA0-BA2 A0-A13 /RAS /CAS CKE0 /WE ODT0
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
SDA
Clock Input
SDRAMs
CK0, /CK0
CK1, /CK1
CK2, /CK2
3
3
3
D8
A1
SDRAMS D0-7,D8 SDRAMS D0-7,D8 SDRAMS D0-7,D8 SDRAMS D0-7,D8
SDRAMS D0-7,D8 SDRAMS D0-7,D8 SDRAMS D0-7,D8
V DD SPD V DD /V DDQ V REF V SS
Serial PD DO-D8 DO-D8 DO-D8
Notes: 1. DQ,DM,DQS,/DQS resistors : 22 +/- 5 %. 2. Bax,Ax,/RAS,/CAS,/WE resistors : 5.1 +/- 5 %.
Rev. 0.3 / Nov. 2008
8
1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM 2GB(256Mbx64) - HMP125U6EFR8C
/S1
/S0
/ DQS0 DQS0 DM0
DM /CS DQS /DQS /
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ DQS4 DQS4 DM4
DM /CS DQS /DQS DM /CS DQS /DQS DM
I/ O 0 I/ O 1 I/ O 2
/CS
DQS /DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D0
D8
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 / DQS5 DQS5 DM5
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D4
I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D12
/ DQS1 DQS1 DM1
DM /CS DQS /DQS
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/CS
DQS /DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 / DQS2 DQS2 DM2
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D1
D9
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 / DQS6 DQS6 DM6
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D5
D13
DM
/CS
DQS /DQS
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/CS
DQS /DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 / DQS3 DQS3 DM3
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D2
D10
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 / DQS7 DQS7 DM7
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D6
D14
DM
/CS
DQS /DQS
DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/CS
DQS /DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D3
D11
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D7
D15
BA0-BA2 A0-A15 CKE0 CKE1 /CAS /RAS
/WE ODT0 ODT1
SDRAMS D0-D15 SDRAMS D0-D15 SDRAMS D0-D7 SDRAMS D8-D15 SDRAMS D0-D15 SDRAMS D0-D15 SDRAMS D0-D15 SDRAMS D0-D7 SDRAMS D8-D15
SCL
SCL WP A0 SA0 Serial PD A1 SA1
SDA
Clock Signal Loads
Clock Input
SDRAMs
4
A1 SA2
CK0, /CK0
CK1, /CK1
VDD SPD VDD /V DDQ VREF VSS Serial PD DO-D15
6
CK2, /CK2
6
DO-D15 DO-D15
Notes: 1. DQ,DM,DQS,/DQS resistors : 22 +/- 5 %. 2. Bax,Ax,/RAS,/CAS,/WE resistors : 7.5 +/- 5 %.
Rev. 0.3 / Nov. 2008
9
1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM 2GB(256Mbx72) - HMP125U7EFR8C
/S1
/S0
/ DQS0 DQS0 DM0
DM / CS DQ S / DQ S
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 DM / CS DQ S / DQ S
/ DQS4 DQS4 DM4
DM / CS DQ S / DQ S
DM I/ O 0 I/ O 1 I/ O 2
/ CS
DQ S / DQ S
D Q0 D Q1 D Q2 D Q3 D Q4 D Q5 D Q6 DQ7
/ DQS1 DQS1 DM1
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D0
D9
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ 39 / DQS5 DQS5 DM5
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D4
I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D13
DM
/ CS
DQ S / DQ S
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DM
/ CS
DQ S / DQ S
DM
/ CS
DQ S / DQ S
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DM
/ CS
DQ S / DQ S
D Q8 D Q9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 / DQS2 DQS2 DM2
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D1
D10
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ 47 / DQ S6 DQ S6 DM6
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D5
D14
/ CS
DQ S / DQ S
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DM
/ CS
DQ S / DQ S
DM
/ CS
DQ S / DQS
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DM
/ CS
DQ S / DQ S
DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 / DQS3 DQS3 DM3
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D2
D11
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 / DQS7 DQS7 DM7
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D6
D15
DM
/ CS
DQ S / DQ S
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DM
/ CS
DQ S / DQ S
DM
/ CS
DQ S / DQ S
DM I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS
DQ S / DQ S
DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
/ DQS8 DQS8 DM8
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D3
D12
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ 63
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D7
D 16
V D D S PD
Serial PD DO-D 17 DO-D 17 DO-D 17
Clock Signal Loads
C lock Input
SD RAM s
DM
/ CS
DQ S / DQ S
I/ O 0 I/ O 1 I/ O 2
DM
/ CS
DQ S / DQ S
V DD /V D DQ V REF
C B0 C B1 C B2 C B3 C B4 C B5 C B6 CB7
BA0-BA2 A0-A13 CKE0 CKE1 /CAS /RAS
/W E ODT0 ODT1
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
CK0, /C K0
CK1, /C K1
CK2, /C K2
6
6
6
D8
I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D17
S CL
VSS
SCL WP A0 S erial PD A1 S A1
A1 SA2
SDA
SDR AM S D 0-D 17 SDR AM S D0-D 17 SDRAM S D 0-D8 SDR AM S D 9-D 17 SDR AM S D0-D 17 SDR AM S D 0-D 17 SDR AM S D 0-D 17 SD RAM S D0-D8 SDR AM S D9-D 17
SA0
Notes: 1. D Q ,DM ,DQ S,/DQ S resistors : 22 +/- 5 % . 2. Bax,Ax,/R AS,/CAS,/W E resistors : 7.5 +/- 5 % .
Rev. 0.3 / Nov. 2008
10
1240pin DDR2 SDRAM Unbuffered DIMMs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss
Symbol
VDD VDDQ VIN, VOUT
Value
- 1.0 ~ 2.3 - 0.5 ~ 2.3 - 0.5 ~ 2.3
Unit
V V V
Note
1 1 1
Operation Conditions and Environmental Parameters
Parameter
DIMM Operating temperature (ambient) Storage Temperature Storage Humidity (without condensation) DIMM Barometric Pressure (operating & storage) DRAM Component Case Temperature Range
Symbol TOPR
TSTG HSTG PBAR TCASE
Rating 0 ~ +55
-50 ~ +100 5 to 95 105 to 69 0 ~+95
Units oC
oC
Notes
1 1 2 3
% K Pascal
oC
Note:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con ditions for extended periods may affect reliablility. 2. Up to 9850 ft. 3. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Symbol VDD VDDL VDDQ VREF VTT VDDSPD Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage EEPROM Supply Voltage Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 1.7 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 3.6 Units V V V mV V V Notes 1 1,2 1,2 3,4 5
Note: 1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option. 2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD. 3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 5. VTT of transmitting device must track VREF of receiving device.
Rev. 0.3 / Nov. 2008
11
1240pin DDR2 SDRAM Unbuffered DIMMs INPUT DC LOGIC LEVEL
Parameter
dc Input logic HIGH dc Input logic LOW
Symbol
VIH(DC) VIL(DC)
Min
VREF + 0.125 -0.30
Max
VDDQ + 0.3 VREF - 0.125
Unit
V V
Note
INPUT AC LOGIC LEVEL
DDR2 400, 533 Parameter Symbol Min
AC Input logic High AC Input logic Low VIH(AC) VIL(AC) VREF + 0.250 -
DDR2 667, 800 Unit Note Min
VREF + 0.200 -
Max
VREF - 0.250
Max
VREF - 0.200 V V
AC INPUT TEST CONDITIONS
Symbol
VREF VSWING(MAX) SLEW
Condition
Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate
Value
0.5 * VDDQ 1.0 1.0
Units
V V V/ns
Notes
1 1 2, 3
Note:
1. 2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions and VIH (ac) to VIL (ac) on the negative transitions.
VSWING(MAX)
VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
delta TR Rising Slew = VIH(ac) min - VREF delta TR delta TF < Figure: AC Input Test Signal Waveform > VREF - VIL(ac) max
delta TF Falling Slew =
Rev. 0.3 / Nov. 2008
12
1240pin DDR2 SDRAM Unbuffered DIMMs
Differential Input AC logic Level
Symbol
VID (ac) VIX (ac)
Parameter
ac differential input voltage ac differential cross point voltage
Min.
0.5 0.5 * VDDQ - 0.175
Max.
VDDQ + 0.6 0.5 * VDDQ + 0.175
Units
V V
Note
1 2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC).
VDDQ VTR VID VCP VSSQ
< Differential signal levels >
Note:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross.
Crossing point
VIX or VOX
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol
VOX (ac)
Parameter
ac differential cross point voltage
Min.
0.5 * VDDQ - 0.125
Max.
0.5 * VDDQ + 0.125
Units
V
Note
1
Note:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross.
Rev. 0.3 / Nov. 2008
13
1240pin DDR2 SDRAM Unbuffered DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol
VOTR
Parameter
Output Timing Measurement Reference Level
SSTL_18
0.5 * VDDQ
Units
V
Notes
1
Note:
1. The VDDQ of the device under test is referenced.
OUTPUT DC CURRENT DRIVE
Symbol
IOH(dc) IOL(dc)
Parameter
Output Minimum Source DC Current Output Minimum Sink DC Current
SSTl_18
- 13.4 13.4
Units
mA mA
Notes
1, 3, 4 2, 3, 4
Note:
1.VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement.
Rev. 0.3 / Nov. 2008
14
1240pin DDR2 SDRAM Unbuffered DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25C) 512MB: HMP164U6EFR6C
Pin
CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 18 57 42 7 Max 22 63 48 9 Unit
pF pF pF pF
1GB: HMP112U6EFR8C
Pin
CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 22 62 42 6 Max 30 84 64 9 Unit
pF pF pF pF
1GB: HMP112U7EFR8C
Pin
CK, CK CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 22 63 43 6 Max 30 85 66 9 Unit
pF pF pF pF
2GB: HMP125U6EFR8C
Pin
CK, CK CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 22 64 50 8 Max 35 87 88 13 Unit
pF pF pF pF
2GB: HMP125U7EFR8C
Pin
CK, CK CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 23 65 52 9 Max 35 89 92 13 Unit
pF pF pF pF
Note: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only.
Rev. 0.3 / Nov. 2008
15
1240pin DDR2 SDRAM Unbuffered DIMMs
IDD SPECIFICATIONS (TCASE: 0 to 95C)
512MB, 64M x 64 U-DIMM: HMP164U6EFR6C
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD7
C4 (DDR2 533@CL 4)
340 440 40 180 140 100 48 180 620 620 640 40 920
Y5 (DDR2 667@CL 5)
360 460 40 120 160 100 48 200 800 740 660 40 1040
S5/S6 (DDR2 800@CL5&6)
380 480 40 128 180 100 48 220 920 860 680 40 1160
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Note
1
Note: 1. IDD6 current values are guaranted up to Tcase of 85C max.
Rev. 0.3 / Nov. 2008
16
1240pin DDR2 SDRAM Unbuffered DIMMs
IDD SPECIFICATIONS (TCASE: 0 to 95C)
1GB, 128M x 64 U-DIMM: HMP112U6EFR8C
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD7
C4 (DDR2 533@CL 4)
520 600 80 216 280 200 96 360 960 960 1280 80 1400
Y5 (DDR2 667@CL 5)
560 640 80 240 320 200 96 400 1160 1120 1320 80 1560
S5/S6 (DDR2 800@CL5&6)
600 680 80 256 360 200 96 440 1360 1280 1360 80 1840
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Note
1
1GB, 128M x 72 ECC U-DIMM: HMP112U7EFR8C
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD7
C4 (DDR2 533@CL 4)
585 675 90 243 315 225 108 405 1080 1080 1440 90 1575
Y5 (DDR2 667@CL 5)
630 720 90 270 360 225 108 450 1305 1260 1485 90 1755
S5/S6 (DDR2 800@CL 5)
675 765 90 288 405 225 108 495 1530 1440 1530 90 2070
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Note
1
Note: 1. IDD6 current values are guaranted up to Tcase of 85C max.
Rev. 0.3 / Nov. 2008 17
1240pin DDR2 SDRAM Unbuffered DIMMs 2GB, 256M x 64 U - DIMM: HMP125U6EFR8C
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD7
C4 (DDR2 533@CL 4)
800 880 160 432 560 400 192 720 1240 1240 1560 160 1680
Y5 (DDR2 667@CL 5)
880 960 160 480 640 400 192 800 1480 1440 1640 160 1880
S5/S6 (DDR2 800@CL5&6)
960 1040 160 512 720 400 192 880 1720 1640 1720 160 2200
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Note
1
2GB, 256M x 72 ECC U-DIMM: HMP125U7EFR8C
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD7
C4 (DDR2 533@CL 4)
900 990 180 486 630 450 216 810 1395 1395 1755 180 1890
Y5 (DDR2 667@CL 5)
990 1080 180 540 720 450 216 900 1665 1620 1845 180 2115
S5/S6 (DDR2 800@CL5&6)
1080 1170 180 576 810 450 216 990 1935 1845 1935 180 2475
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Note
1
Note: 1. IDD6 current values are guaranted up to Tcase of 85C max.
Rev. 0.3 / Nov. 2008
18
1240pin DDR2 SDRAM Unbuffered DIMMs
IDD MEASUREMENT CONDITIONS
Symbol IDD0 Conditions
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin (IDD);CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin (IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Units
mA
IDD1
mA mA mA mA mA mA mA
IDD2P IDD2Q IDD2N IDD3P
Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85 max.
IDD4W
mA
IDD4R
mA
IDD5B
mA
Normal Low Power mA
IDD6
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
mA
Note: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC (max) HIGH is defined as Vin VIHAC (min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
Rev. 0.3 / Nov. 2008 19
1240pin DDR2 SDRAM Unbuffered DIMMs Electrical Characteristics & AC Timings
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin (CL-tRCD-tRP) Parameter CAS Latency tRCD tRP tRC tRAS
DDR2-800 (S5)
5-5-5 min 5 12.5 12.5 57.5 45
DDR2-800 (S6)
6-6-6 min 6 15 15 45 60
DDR2-667 (Y5)
5-5-5 min 5 15 15 60 45
DDR2-533 (C4)
4-4-4 min 4 15 15 60 45
Unit
ns ns ns ns ns
AC Timing Parameters by Speed Grade
DDR2-400 Parameter
Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew Clock High Level Width Clock Low Level Width Clock Half Period System Clock Cycle Time DQ and DM input setup time DQ and DM input hold time Control & Address input Pulse Width for each input DQ and DM input pulse width for each input pulse width for each input Data-out high-impedance window from CK, /CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write preamble
DDR2-533 Unit Note Min
-500 -500 0.45 0.45 min (tCL, tCH) 3750 100 225 0.6 0.35 tAC min 2*tAC min tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 0.35
Symbol Min
tAC tDQSCK tCH tCL tHP tCK tDS tDH tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRE -600 -500 0.45 0.45 min (tCL, tCH) 5000 150 275 0.6 0.35 tAC min 2*tAC min tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 0.35
Max
600 500 0.55 0.55 8000 tAC max tAC max tAC max 350 450 WL + 0.25 -
Max
500 450 0.55 0.55 8000 tAC max tAC max tAC max 300 400 WL + 0.25 ps ns CK CK ns ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK 1 1
Rev. 0.3 / Nov. 2008
20
1240pin DDR2 SDRAM Unbuffered DIMMs
- continued -
DDR2-400 Parameter
Address and control input setup time Address and control input hold time Read preamble Read postamble Auto-Refresh to Active/Auto-Refresh command period Row Active to Row Active Delay for 1KB page size Row Active to Row Active Delay for 2KB page size Four Activate Window for 1KB page size Four Activate Window for 2KB page size CAS to CAS command delay Write recovery time Auto Precharge Write Recovery + Precharge Time Write to Read Command Delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on (Power-Down mode) ODT turn-off delay ODT turn-off
DDR2-533 Unit Note Min
250 375 0.9 0.4
Symbol Min
tIS tIH tRPRE tRPST tRFC tRRD tRRD tFAW tFAW tCCD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS tCKE tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tOIT tDelay tREFI tREFI 350 475 0.9 0.4
Max
1.1 0.6
Max
1.1 0.6 ps ps tCK tCK
127.5
7.5 10 37.5 50 2 15 tWR + tRP 10 7.5 tRFC + 10 200 2 2 6 - AL 3 2 tAC (min) tAC(min)+2 2.5 tAC (min)
-
127.5
7.5 10 37.5 50 2
-
ns
ns ns ns ns tCK
-
15 tWR + tRP 7.5 7.5 tRFC + 10
-
ns tCK ns ns ns
-
200 2 2 6 - AL 3
-
tCK tCK tCK tCK tCK
2 tAC(max)+1 2tCK+tAC(m ax)+1 2.5 tAC (max)+ 0.6
2 tAC (min) tAC(min)+2 2.5 tAC (min)
2 tAC(max)+1 2tCK+tAC(m ax)+1 2.5 tAC (max)+ 0.6
tCK ns ns tCK ns ns tCK tCK
ODT turn-off (Power-Down mode)
ODT to power down entry latency
tAC(min)+2 3 8 0 tIS + tCK + tIH -
2.5tCK+tA C(max)+1
tAC(min)+2 3 8
2.5tCK+tA C(max)+1
ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval
12
0 tIS + tCK + tIH
12
ns ns
7.8 3.9
-
7.8 3.9
us us
2 3
Note: 1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS1G[8, 16]31CFP). 2. 0C TCASE C C TCASE C
Rev. 0.3 / Nov. 2008
21
1240pin DDR2 SDRAM Unbuffered DIMMs
Parameter
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time
(differential strobe)
Symbol
tAC tDQSCK tCH tCL tHP tCK tDS tDH tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRE tWPST tIS tIH tRPRE tRPST
tRFC
DDR2-667 min
-450 -400 0.45 0.45 min(tCL, tCH) 3000 100 175 0.6 0.35 tAC min 2*tAC min tHP - tQHS - 0.25 0.35 0.35 0.2 0.2 2 0.35 0.4 200 275 0.9 0.4 127.5 7.5 10 37.5 50
DDR2-800 min
-400 -350 0.45 0.45 min(tCL, tCH) 2500 50 125 0.6 0.35 tAC min 2*tAC min tHP - tQHS - 0.25 0.35 0.35 0.2 0.2 2 0.35 0.4 175 250 0.9 0.4 127.5 7.5 10 35 45 tAC max tAC max tAC max 200 300 + 0.25 0.6 1.1 0.6 -
max
+450 +400 0.55 0.55 8000 tAC max tAC max tAC max 240 340 + 0.25 0.6 1.1 0.6 -
max
+400 +350 0.55 0.55 -
Unit Note
ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns ns ns ns ns 1 1
DQ and DM input hold time
(differential strobe)
Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write preamble Write postamble Address and control input setup time Address and control input hold time Read preamble Read postamble
Auto-Refresh to Active/Auto-Refresh command period
Active to active command period for 1KB page size products Active to active command period for 2KB page size products Four Active Window for 1KB page size products Four Active Window for 2KB page size products
tRRD tRRD tFAW tFAW
Rev. 0.3 / Nov. 2008
22
1240pin DDR2 SDRAM Unbuffered DIMMs
- continued Parameter
CAS to CAS command delay Write recovery time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on (Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval
Symbol
tCCD tWR tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS tCKE tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tOIT tDelay
tREFI tREFI
DDR2-667 min
2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 7 - AL 3 2 tAC (min) tAC(min)+2 2.5 tAC (min) tAC (min) +2 3 8 0 tIS + tCK + tIH 7.8 3.9 12 2 tAC (max) +0.7 -
DDR2-800 min
2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 8 - AL 3 2 tAC (min) 2 tAC (max) +0.7 -
max
max
Unit Note
tCK ns tCK ns ns ns tCK tCK tCK tCK tCK tCK ns ns tCK ns ns tCK tCK
Auto precharge write recovery + precharge time tDAL
2tCK+ tAC (min) 2tCK+ tAC(max)+1 +2 tAC(max)+1 2.5 tAC (max)+ 0.6 2.5 tAC (min) 2.5 tAC (max) +0.6
2.5tCK+ tAC (min) 2.5tCK+ tAC(max)+1 +2 tAC(max)+1 3 8 0 tIS + tCK + tIH 7.8 3.9 12
ns ns us us 2 3
Note: 1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS1G[8,16]31CFP). 2. 0C TCASE C C TCASE C
Rev. 0.3 / Nov. 2008
23
1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE 64Mx 64 - HMP164U6EFR6C
4.00.1
(Front)
1. 27 0.10
0.20
0.05
0.10
Rev. 0.3 / Nov. 2008
24
1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE 128Mx 64 - HMP112U6EFR8C
(Front)
4.00.1
1. 27
0.10
0.20
0.05
0.10
Rev. 0.3 / Nov. 2008
25
1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE 128Mx 72 - HMP112U7EFR8C
(Front)
4.00.1
1. 27
0.10
0.20 0.05
0.10
Rev. 0.3 / Nov. 2008
26
1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE 256Mx 64 - HMP125U6EFR8C
4.00.1
0.20 0.05
0.10
Rev. 0.3 / Nov. 2008
27
1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE 256Mx 72 - HMP125U7EFR8C
4.00.1
0.20 0.05
0.10
Rev. 0.3 / Nov. 2008
28
1240pin DDR2 SDRAM Unbuffered DIMMs REVISION HISTORY
Revision 0.1 0.2 0.3 History Initial data sheet released Editorial Correction Corrected Block Diagram Date Jun. 2008 Sep. 2008 Nov. 2008
Rev. 0.3 / Nov. 2008
29

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